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#uml IRC Logs for 2007-01-02

---Logopened Tue Jan 02 00:00:14 2007
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10:26<jdike>Hi guys
10:53<caker>jdike: Happy New Year
10:55<jdike>You too
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10:58<caker> <-- jdike, make any sense to you?
11:01<jdike>WTF is a UML trying to create an ISA bounce pool?
11:04<caker>heh .. also,
11:10<jdike>Oh yeah
11:11<jdike>what config do you need to turn on in order to get this?
11:13<caker>my config is in a post to that thread above
11:24<jdike>I see you switched the IO scheduler
11:24<jdike>does that get rid of scheduler-related crashes?
11:31<caker>No reports of that yet
11:32<jdike>still chasing that bug
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12:01<the_hydra>jdike: happy new year 2007
12:02<the_hydra>jdike: do you know that your UML book is "leaked" on the Net already?
12:03<jdike>BTW, what form is it?
12:03<jdike>scanned pages, or an electronic form?
12:03<the_hydra>ok, I tried to let you know about it days ago but I couldn't meet you in this chanel
12:03<the_hydra>HTML based
12:03<the_hydra>/msg jdike
12:04<the_hydra>arrgh, that was supposed to be a pm
12:05<the_hydra>if I am allowed to suggest, I think you better tell the publisher to made it available legally on Net, something like LDD2/3
12:05<jdike>this must have come from the publisher
12:06<jdike>they are the only ones who have a form that could have been turned into that web site
12:06<the_hydra>hm ok
12:06<jdike>unless someone bought the book and typed it all in
12:06<jdike>and it is available under some sort of open license
12:06<the_hydra>well,that's all I can tell you, I hope this info is helpful
12:06<jdike>the whole series is
12:06<the_hydra>Bruce perens, right?
12:07<the_hydra>or Pearson?
12:07<jdike>I personally don't have a problem with this - it might cost me some royalties, but that's not going to be a lot anyway
12:07<jdike>it's the publisher that wants to make some money from this
12:08<the_hydra>yes I do think so too
12:09<the_hydra>I knew that link when searching for blog post related to UML in technorati
12:09<the_hydra>was finding info about how TT and SKAS work
12:11<the_hydra>jdike: I have some basic questions about TT mode
12:11<the_hydra>jdike: how do you map the UML kernel into the upper space of process address space?
12:14<jdike>sorry, wrong question
12:14<jdike>that's done with the linker script
12:14<jdike>it specifies the load address
12:15<the_hydra>oh I see
12:16<the_hydra>nowonder I didn't see something like mmap()-ing into certain address
12:16<the_hydra>ok, I also checked the linker script, so perhaps I need to study more about ld
12:19<jdike>the info page has script documentation
12:20<the_hydra>reading that too, thanks
12:22<the_hydra>and in TT mode, since the UML kernel is mapped to each host process address space, there is no need to switch address space, it just intercept the syscall, jump into UML kernel and possibly request something to host kernel...pls cmiiw
12:23<jdike>it's a bit more complicated than that, but that
12:23<jdike>'s basically right
12:24<the_hydra>jdike: reading codes inside arch/um is not an easy task for a newbie like me :)
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12:25<jdike>it wasn't any fun to write, either
12:26<the_hydra>jdike: well, but I appreciate on what you do with UML... :)
12:30<the_hydra>jdike: in SKAS0, technically how to separate kernel address space with normal process address space without host kernel support? by simply creating another process strictly to map UML kernel?
12:30<jdike>you get new address spaces by creating new processes
12:34<jdike>although that's kinda backwards
12:34<jdike>the kernel address space exists from the start, when you run UML
12:34<jdike>it's the other address spaces that need special treatment
12:37<the_hydra>oh sorry, wait, in SKAS0, UML kernel isn't fully mapped to user address space, I saw there is somekind of "vsyscall" page mapped into the upper user space address..
12:38<the_hydra>and within this page, there is a code to do the jump into kernel?
12:38<jdike>that can't be allowed
12:38<jdike>because if it could be done from there, it could be done from anywhere in the process
12:39<jdike>transfers from there to the kernel are done with signals
12:39<the_hydra>oh right signal
12:39<jdike>when the child gets a signal, that's seen by the kernel
12:39<jdike>so it knows when the child has finished collecting page fault data or remapping its address space
12:40<the_hydra>hm, ptrace catch the signal, and the process enter UML kernel address space?
12:40<jdike>not really
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12:40<jdike>you can think of control flow entering the UML kernel
12:40<jdike>but the process stays right where it is until it's continued
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13:23<caker>jdike: so what action should I take to get rid of that ISA thing -- back out that patch?
13:23<caker>jdike: is that something you're going to send upstream?
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13:25<jdike>just back out the patch
13:25<jdike>I need to figure out what it broke and fix that
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13:54<the_hydra>jdike: frozen because of ptrace trap?
14:38<jdike>Oh, you mean the child?
14:39<the_hydra>yes, I meant the child :)
14:39<the_hydra>sorry if I wasn't clearly mention it
14:40<the_hydra>I didn't remember if I already asked about it or UML simulate the PIT? by simply using setitimer to deliver signal ?
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---Logclosed Wed Jan 03 00:00:20 2007